![]() It will have all the details – TB architecture, Coverage Model, Verification Strategy, etc. It acts as a golden reference document for all the verification folks who are responsible for the complete verification sign-off. It captures all the design features and defines how each feature can be verified and tracked closely. ![]() Verification Plan: Defines the verification intent of the DUV. Let me share some of the important guidelines to implement a VIP. So, the reusable testbenches that follow a standard methodology, TB architecture and coding guidelines are called Verification IPs. ![]() Also, if the testbench will be used by any third party to verify their IP/Chip, then the testbench should comply with coding guidelines as per the methodology like UVM. We always want to use the same module/IP level testbench to verify the IP’s derivatives or the same IP at the chip /SoC level too. Most of the module/IP level testbenches are used once to verify the design. Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP.
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